PRO3: A Hybrid NPU Architecture
IEEE Micro
A pattern matching coprocessor for network security
Proceedings of the 42nd annual Design Automation Conference
Didactic architectures and simulator for network processor learning
WCAE '03 Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture
Reconfigurable architecture for network flow analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and performance evaluation of an adaptive FPGA for network applications
Microelectronics Journal
Customizing virtual networks with partial FPGA reconfiguration
Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures
Customizing virtual networks with partial FPGA reconfiguration
ACM SIGCOMM Computer Communication Review
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present an accelerator that is designed to improve performance of network processing applications, particularly layer seven networking applications. The accelerator can easily be integrated in Network Processors. We present the design details of two different FPGA implementations: a design where each task is implemented in the accelerator and another one where the accelerator must be partially reconfigured for different tasks. We also present novel algorithms for important tasks such as tree lookup and pattern matching that utilize the accelerator. We show that the accelerator improves the overall execution time by as much as 20-times for these tasks. We show that the accelerator can improve the execution time of a representative layer seven application by an order of magnitude. Finally, we discuss the effects of reconfiguration time and frequency over the performance of the accelerator.