Reprogrammable network packet processing on the field programmable port extender (FPX)
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Computer Networks: The International Journal of Computer and Telecommunications Networking - Special issue on programmable networks
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A secure adaptive network processor
A secure adaptive network processor
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architecture and Application of PLATO, A Reconfigurable Active Network Platform
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Analysis of a reconfigurable network processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Wide-area Internet traffic patterns and characteristics
IEEE Network: The Magazine of Global Internetworking
Feasibility study of a self-healing hardware platform
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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This paper presents the design, implementation and performance evaluation of a coarse-grain dynamically reconfigurable FPGA platform for multi-service edge and access network devices. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of packet payloads (Data Encryption Standard (DES) and Lempel-Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The functionality of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented on the Xilinx Virtex II Pro platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the network traffic fluctuation.