Interface specification for reconfigurable components
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A reconfigurable logic-based processor for the SCAN image and video encryption algorithm
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster
Cluster Computing
Design and performance evaluation of an adaptive FPGA for network applications
Microelectronics Journal
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A new, configurable architecture has been designed and built in order to serve as a platform for experimentation with active networks. This architecture, named PLATO, provides 4 physical bi-directional connections for ATM networks, large reconfigurable resources, 256 Mbytes SDRAM for buffer space, a PCI port, and auxiliary expansion ports. Several applications are presented for this platform, one of which has been prototyped on the PCI Pamette and on PLATO. Detailed simulations and experimental results show that, for some applications, a significant improvement can be obtained using this approach as compared to using conventional network architectures.