A reconfigurable logic-based processor for the SCAN image and video encryption algorithm

Authors:
C. Kachris;N. Bourbakis;A. Dollas
Affiliations:
Department of Electronic and Computer Engineering, Technical University of Crete, 73100 Chania, Greece;Information Technology Research Institute, Wright State University, Dayton, Ohio;Department of Electronic and Computer Engineering, Technical University of Crete, 73100 Chania, Greece
Venue:
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Year:
2003

Citing 9
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Abstract

This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64 × 64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.