Reconfigurable architecture for network flow analysis

Authors:
S. Yusuf;W. Luk;M. Sloman;N. Dulay;E. C. Lupu;G. Brown
Affiliations:
Department of Computing, Imperial College London, London, U.K.;Department of Computing, Imperial College London, London, U.K.;Department of Computing, Imperial College London, London, U.K.;Department of Computing, Imperial College London, London, U.K.;Department of Computing, Imperial College London, London, U.K.;Department of Computer Science, Indiana University, Bloomington, IN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high network data rates. Our approach maps the performance-critical tasks of packet classification and flow monitoring into reconfigurable hardware, such that multiple flows can be processed in parallel We explore the scalability of our system, showing that it can support flows at multi-gigabit rate; this is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits per second.