High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
IEEE/ACM Transactions on Networking (TON)
Link-sharing and resource management models for packet networks
IEEE/ACM Transactions on Networking (TON)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Difficulties in simulating the internet
IEEE/ACM Transactions on Networking (TON)
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Principles and Practices of Interconnection Networks
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Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset
IEEE Communications Magazine
IEEE Communications Magazine
A practical architecture for implementing end-to-end QoS in an IP network
IEEE Communications Magazine
A framework for optimizing the cost and performance of next-generation IP routers
IEEE Journal on Selected Areas in Communications
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
On the speedup required for work-conserving crossbar switches
IEEE Journal on Selected Areas in Communications
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
A distributed scheduling architecture for scalable packet switches
IEEE Journal on Selected Areas in Communications
Credit-based flow control for ATM networks
IEEE Network: The Magazine of Global Internetworking
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Packet-switch fabrics with widely varying characteristics are currently deployed in the domains of both communications and computer interconnection networks. For economical reasons, it would be highly desirable that a single switch fabric could accommodate the needs of a variety of heterogeneous services and applications from both domains. In this paper, we consider the current requirements, technological trends, and their implications on the design of an ASIC chipset for a merchant switch fabric. We then identify the architecture upon which such a suitable and generic switch fabric could be based, and we present the general characteristics of an implementation of this switching fabric within the bounds of current state-of-the-art technology. To our knowledge, this is the first attempt to design a chipset that can be used for both communications and computer interconnection networks.