Journal of High Speed Networks
Concurrent round-robin-based dispatching schemes for Clos-network switches
IEEE/ACM Transactions on Networking (TON)
Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches
IWDC '01 Proceedings of the Thyrrhenian International Workshop on Digital Communications: Evolutionary Trends of the Internet
ICN '01 Proceedings of the First International Conference on Networking-Part 1
Dispatching schemes for Clos-network switches
Computer Networks: The International Journal of Computer and Telecommunications Networking
Captured-frame matching schemes for scalable input-queued packet switches
Computer Communications
Design issues in next-generation merchant switch fabrics
IEEE/ACM Transactions on Networking (TON)
Review: Review of recent shared memory based ATM switches
Computer Communications
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The ATLANTATM switching architecture has the following distinguishing characteristics: (1) is nonblocking, (2) scales modularly over a wide range of switching and buffering capacities using commonly available implementation technology, (3) achieves high buffer utilization while using distributed buffers, (4) has low complexity, and (5) provides a clear path for future growth in features. The ATLANTA architecture uses an innovative structure with ingress and egress buffers, where selective backpressure is applied from the fabric to the ingress cards. Selective backpressure makes the buffers in the ingress cards act as an extension of the output buffers in the fabric, achieving "sharing" of the distributed buffers and buffer utilization comparable with a centralized shared-memory switch. The advantage is that the majority of the buffers are in the ingress and egress port cards, and are implemented using low-cost off-the-shelf memories regardless of the total switching capacity. Different arrangements are possible for the switch fabric. In the smallest configuration, the fabric consists of a single standalone switching module; for larger switching capacities, the fabric is a modular three-stage memory/space/memory (MSM) arrangement. The ATLANTA architecture provides optimal support of multicast traffic. The ATLANTA chipset provides the complete set of building blocks for implementing ATM switches ranging in capacity from 622 Mb/s to 25 Gb/s. The chipset consists of four chips, two devices to be used in the fabric and two in the port cards. The port devices provide full-duplex ingress and egress functionality at 622 Mb/s port rate (plus the overhead due to the local header used internally to the switch). The physical interface to the incoming/outgoing lines supports the UTOPIA II multiplexing standard, and the port devices manage multiplexing/demultiplexing from/to a maximum of 30 subports per port. Although our current implementation of the architecture is targeted primarily to ATM, the principles behind the architecture are more general, and apply to IP switching and routing technologies.