High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Journal of High Speed Networks - Special issue on optical networking
Switching and Traffic Theory for Integrated Broadband Networks
Switching and Traffic Theory for Integrated Broadband Networks
Concurrent round-robin-based dispatching schemes for Clos-network switches
IEEE/ACM Transactions on Networking (TON)
Design of a Gigabit ATM Switch
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Parallel routing algorithms in Benes-Clos networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset
IEEE Communications Magazine
A distributed scheduling architecture for scalable packet switches
IEEE Journal on Selected Areas in Communications
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The Clos-network is widely recognized as a scalable architecture for high-performance switches and routers. The ATLANTA switch with its Memory/Space/Memory (MSM) architecture constitutes a commercially successful example. The CRRD and CMSD dispatching/arbitration algorithms have been recently proposed for the MSM Clos-network switches, by using simple round-robin arbiters. Based on the Static Round-Robin (SRR) technique, we propose the SRRD arbitration algorithm for the MSM Clos-network switches. The intuition behind the SRR technique is to desynchronize the pointers of the arbiters in a static way and hence considerably improve the delay performance. However, the MSM architecture is accompanied with a memory speedup problem. As a result, we propose a highly scalable Bufferless Clos-network switching architecture to address this issue. Based on the SRR technique again, we develop the Distro dispatching algorithm for the new architecture. We demonstrate by simulation that Distro can achieve 100% throughput under uniform traffic. The delay performance of Distro in the Bufferless Closnetwork architecture is comparable to that of conventional algorithms in crossbar switches.