High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
IEEE/ACM Transactions on Networking (TON)
Hierarchical packet fair queueing algorithms
Conference proceedings on Applications, technologies, architectures, and protocols for computer communications
General Methodology for Designing Efficient Traffic Scheduling and Shaping Algorithms
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Backpressure in shared-memory-based ATM switches under multiplexed bursty sources
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset
IEEE Communications Magazine
Traffic management for an ATM switch with per-VC queuing: concept and implementation
IEEE Communications Magazine
Multicast scheduling for input-queued switches
IEEE Journal on Selected Areas in Communications
A distributed scheduling architecture for scalable packet switches
IEEE Journal on Selected Areas in Communications
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Multi-stage packet switches that feature a limited amount of buffers in the switching fabric and distribute most of their buffering capacity over the port cards have recently gained popularity due to their scalability properties and flexibility in supporting Quality-of-Service (QoS) guarantees. In such switches, the replication of multicast packets typically occurs at the outputs of the switching fabric. This approach minimizes the amount of resources needed to sustain the internal expansion in traffic volume due to multicasting, but also exposes multicast flows to head-of-line (HOL) blocking in the ingress port cards. Access regulation to the fabric buffers is of the utmost importance to safeguard the QoS of multicast flows against HOL blocking. We add minimal overhead to a well-known distributed scheduler for multi-stage packet switches to define the Generalized Distributed Multi-layered Scheduler (G-DMS), which achieves full support of QoS guarantees for both unicast and multicast flows. The novelty of the G-DMS is in the mechanism that regulates access to the fabric buffers, which combines selective backpressure with the capability of dropping copies of multicast packets that violate the negotiated profiles of the corresponding flows.