Performance modelling of a multi-buffered Banyan switch under bursty traffic
IEEE INFOCOM '92 Proceedings of the eleventh annual joint conference of the IEEE computer and communications societies on One world through communications (Vol. 1)
Analysis of input and output queueing for nonblocking ATM switches
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Two-dimensional round-robin schedulers for packet switches with multiple input queues
IEEE/ACM Transactions on Networking (TON)
Sharing memory in multistage ATM switches
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Performance of a Three-Stage Banyan-Based Architecture with Input and Output Buffers for Large Fast Packet Switches
Dynamic queue length thresholds in a shared memory ATM switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
A new buffer management scheme for hierarchical shared memory switches
IEEE/ACM Transactions on Networking (TON)
Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches
IWDC '01 Proceedings of the Thyrrhenian International Workshop on Digital Communications: Evolutionary Trends of the Internet
Review: Review of recent shared memory based ATM switches
Computer Communications
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In this paper, we study a shared-memory center-stage switch with input multiplexers and output demultiplexers, where backpressure is applied from the demultiplexers to the center stage, and from the center stage to the multiplexers. We consider three backpressure schemes: i) Non-Selective Backpressure (NSB), where a congested center stage or a congested demultiplexer applies backpressure indiscriminately to all the traffic destined to it, regardless of the destination: ii) Per-Port Selective Backpressure (PPSB), where the center stage applies backpressure selectively only to the traffic destined to the center-stage port(s) experiencing congestion, but a demultiplexer applies backpressure indiscriminately to all the traffic destined to it; and iii) Per-Subport Selective Backpressure (PSSB), where both center-stage switch and demultiplexers apply backpressure selectively only to the traffic destined to the output link(s) experiencing congestion. We show that NSB introduces heavy HOL blocking which limits the throughput of the system and causes heavy losses. On the contrary, PPSB and PSSB achieve high throughputs, and allow to increase buffer utilization in the system while keeping the majority of the buffers physically separate in the input multiplexers, a very desirable feature when implementing systems with large buffer capacity. Both these schemes perform very well in the case where only limited sharing of the buffers in the center stage is allowed, as required to guarantee fairness in the switch. With PSSB, small buffer sizes in the demultiplexers can be used. If the buffers in the demultiplexers are large, PPSB and PSSB offer comparable performance.