The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Alpha 21364 Network Architecture
IEEE Micro
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
Fair queueing based packet scheduling for buffered crossbar switches
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Packet-mode asynchronous scheduling algorithm for partially buffered crossbar switches
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
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As Systems-on-a-Chip (SoCs) become larger, the problem of interconnecting the various subsystems becomes more complicated. In this framework, certain alternatives to the standard buses, based on Network Technologies, have emerged as innovative approaches for SoC's interconnect. One of the main advantages of such an alternative, is that it can offer certain Quality of Service (QoS) over the internal cross-connects while at the same time it supports higher transfer rates than the existing on-chip buses. This paper presents the first chip interconnection architecture, which is based on a buffered crossbar switch. The main advantage of the proposed system is that it efficiently supports different priority levels; it also provides several Gigabits per Second of aggregate bandwidth, while it introduces very low latency. Moreover, the hardware complexity of this highly scalable scheme is minimal. All those facts make this framework ideal for SoCs that contain IP cores with diverse speed/throughput requirements.