Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round-robin
IEEE/ACM Transactions on Networking (TON)
Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Computer Networking: A Top-Down Approach (4th Edition)
Computer Networking: A Top-Down Approach (4th Edition)
A buffered crossbar-based chip interconnection framework supporting quality of service
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exact GPS simulation and optimal fair scheduling with logarithmic complexity
IEEE/ACM Transactions on Networking (TON)
Max-Min Fair Scheduling in Input-Queued Switches
IEEE Transactions on Parallel and Distributed Systems
On guaranteed smooth switching for buffered crossbar switches
IEEE/ACM Transactions on Networking (TON)
Localized Independent Packet Scheduling for Buffered Crossbar Switches
IEEE Transactions on Computers
Fair Round-Robin: A Low Complexity Packet Schduler with Proportional and Worst-Case Fairness
IEEE Transactions on Computers
Strong performance guarantees for asynchronous buffered crossbar scheduler
IEEE/ACM Transactions on Networking (TON)
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Packet-level traffic measurements from the Sprint IP backbone
IEEE Network: The Magazine of Global Internetworking
| Hi-index | 0.00 |
Recent development in VLSI technology makes it feasible to integrate on-chip memories to crossbar switching fabrics. Switches using such crossbars are called buffered crossbar switches, in which each crosspoint has a small exclusive buffer. The crosspoint buffers decouple input ports and output ports, and reduce the switch scheduling problem to the fair queueing problem. In this paper, we present the fair queueing based packet scheduling scheme for buffered crossbar switches, which requires no speedup and directly handles variable length packets without segmentation and reassembly (SAR). The presented scheme makes scheduling decisions in a distributed manner, and provides performance guarantees. Given the properties of the actual fair queueing algorithm used in the scheduling scheme, we calculate the crosspoint buffer size bound to avoid overflow, and analyze the fairness and delay guarantees provided by the scheduling scheme. In addition, we use WF2Q, the fair queueing algorithm with the tightest performance guarantees, as a case study, and present simulation data to verify the analytical results.