Communication networks: a first course
Communication networks: a first course
On the self-similar nature of Ethernet traffic
SIGCOMM '93 Conference proceedings on Communications architectures, protocols and applications
Self-similarity in World Wide Web traffic: evidence and possible causes
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Modeling and simulation of steady state and transient behaviors for emergent SoCs
Proceedings of the 14th international symposium on Systems synthesis
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
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We present the modeling of the high-level design of a next generation network switch from the perspective of a Computer-Aided Design (CAD) team within the larger context of a design team consisting of an experienced network switch designer and an experienced VLSI hardware designer. After facilitating the design process, the CAD team observed how designers approach high-level designs, beyond RTL. We motivate the need for CAD support that allows designers to effectively manipulate what we refer to as Memory Visualization Level (MVL) design.