FPGA Implementations of Neural Networks
FPGA Implementations of Neural Networks
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
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This paper describes the development of a framework for prototyping evolvable hardware Spiking Neural Networks using runtime reconfigurable systems in a Xilinx FPGAs. Practical implementations are focused on the classification of acquired EEG signals that are processed using the wavelet transform. The dynamic run-time partial reconfiguration (PR) capability of the Virtex FPGA is used to interchange those units of the system -- therefore saving precious resources -- that do not run their algorithms in parallel.