Implementation of pulsed neural networks in CMOS VLSI technology
ISPRA'05 Proceedings of the 4th WSEAS International Conference on Signal Processing, Robotics and Automation
Review article: Review of pulse-coupled neural networks
Image and Vision Computing
A neuron-MOS-based VLSI implementation of pulse-coupled neural networks for image feature generation
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents a compact architecture for analog CMOS hardware implementation of voltage-mode pulse-coupled neural networks (PCNN). The hardware implementation methods shows inherent fault tolerance specialties and high speed, which is usually more than an order of magnitude over the software counterpart. A computational style described in this article mimics a biological neural network using pulse-stream signaling and analog summation and multiplication, pulse-stream encoding technique uses pulse streams to carry information and control analog circuitry, while storing further analog information on the time axis. The main feature of the proposed neuron circuit is that the structure is compact, yet exhibiting all the basic properties of natural biological neurons. Functional and structural forms of neural and synaptic functions are presented along with simulation results. Finally, the proposed design is applied to image processing to demonstrate successful restoration of images and their features