A neuron-MOS-based VLSI implementation of pulse-coupled neural networks for image feature generation

Authors:
Jun Chen;Tadashi Shibata
Affiliations:
Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan;Department of Electrical Engineering and Information Systems, The University of Tokyo, Chiba, Japan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

An analog circuit for implementing pulse-coupled neural networks (PCNNs) in very-large-scale integration (VLSI) hardware has been developed using the Neuron-MOS (νMOS) technology. PCNNs are biologically inspired models having powerful ability for image feature generation. With the νMoS technology, weighted sum of multiple input signals, which is an essential of PCNNs, is implemented simply by the capacitive coupling effect in a νMOS block. By employing the switched floating gates in the νMOS blocks as temporary analog memories, the storage of image data is simply realized. Moreover, the function of decay generation, which is crucial for emulating PCNNs neuronal dynamics, is also merged into a νMOS block by utilizing the input-terminal capacitors in it. With such techniques, the circuit achieves a purely voltage-mode implementation of PCNNs in a compact structure. Inheriting the merits of PCNNs, the circuit has good discriminability against different patterns as well as robustness against rotation and translation of identical patterns, which is analogous to human image perception. The performance of the circuit has been verified by the measurements of a proof-of-concept chip fabricated in a O.35-µm double-polysilicon CMOS technology.