Analog VLSI and neural systems
Analog VLSI and neural systems
Learning in neural networks with material synapses
Neural Computation
An analog memory circuit for spiking silicon neurons
Neural Computation
Floating-gate MOS synapse transistors
Neuromorphic systems engineering
Analog versus digital: extrapolating from electronics to neurobiology
Neural Computation
Temporally asymmetric Hebbian learning, spike timing and neuronal response variability
Proceedings of the 1998 conference on Advances in neural information processing systems II
Neurophysiology of a VLSI Spiking Neural Network: LANN21
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 3 - Volume 3
A spiking neuron model: applications and learning
Neural Networks
Spike-Driven Synaptic Plasticity for Learning Correlated Patterns of Asynchronous Activity
ICANN '02 Proceedings of the International Conference on Artificial Neural Networks
Dynamics of a Plastic Cortical Network
ICANN '02 Proceedings of the International Conference on Artificial Neural Networks
Spike-driven synaptic dynamics generating working memory states
Neural Computation
Attractor Networks for Shape Recognition
Neural Computation
Synaptic Dynamics in Analog VLSI
Neural Computation
Optimizing one-shot learning with binary synapses
Neural Computation
Spiking neural networks for reconfigurable POEtic tissue
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Recognition of partially occluded and rotated images with a network of spiking neurons
IEEE Transactions on Neural Networks
WCCI'12 Proceedings of the 2012 World Congress conference on Advances in Computational Intelligence
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We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takàcs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (∼100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are low and LTP is balanced against LTD.