Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
The BSB model: a simple nonlinear autoassociative neural network
Associative neural memories
NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices
Proceedings of the conference on Design, automation and test in Europe - Volume 3
On Intelligence
2005 Special Issue: On-chip visual perception of motion: A bio-inspired connectionist model on FPGA
Neural Networks - 2005 Special issue: IJCNN 2005
Towards cortex sized artificial neural systems
Neural Networks
A preliminary investigation of a neocortex model implementation on the Cray XD1
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Anatomy of a cortical simulator
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
A computational model of the cerebral cortex
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 2
Why Can't a Computer be more Like a Brain?
IEEE Spectrum
Self-organizing learning array
IEEE Transactions on Neural Networks
Cortical architectures on a GPGPU
Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
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This paper presents the implementation and scaling of a neocortex inspired cognitive model on a Cray XD1. Both software and reconfigurable logic based FPGA implementations of the model are examined. This model belongs to a new class of biologically inspired cognitive models. Large scale versions of these models have the potential for significantly stronger inference capabilities than current conventional computing systems. These models have large amounts of parallelism and simple computations, thus allowing highly efficient hardware implementations. As a result, hardware-acceleration of these models can produce significant speedups over fully software implementations. Parallel software and hardware-accelerated implementations of such a model are investigated for networks of varying complexity. A scaling analysis of these networks is presented and utilized to estimate the throughput of both hardware-accelerated and software implementations of larger networks that utilize the full resources of the Cray XD1. Our results indicate that hardware-acceleration can provide average throughput gains of 75 times over software-only implementations of the networks we examined on this system.