The TInMANN VLSI chip

Authors:
M. Melton;T. Phan;D. S. Reeves;D. E. Van den Bout
Affiliations:
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC;-;-;-
Venue:
IEEE Transactions on Neural Networks
Year:
1992

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Abstract

A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size. The neuron operates at a speed of 15 MHz, making it capable of processing 195000 three-dimensional training examples per second. Three man-months were required to synthesize the neuron and its associated level-sensitive scan logic using the OASIS silicon compiler. The ease of synthesis allowed many performance trade-offs to be examined, while the automatic testability features of the compiler helped the designers achieve 100% fault coverage of the chip. These factors served served to create a fast, dense, and reliable neural chip