SOM Hardware with Acceleration Module for Graphical Representation of the Learning Process
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
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Selforganizing Feature Maps (SOFMs) can be applied for data analysis, controlling problems and pattern matching. In many cases the requirements of a system using these maps are high performance and small physical size. This leads to the necessity of custom chip designs. In this paper two chips are presented, that realize a scalable processor array for selforganizing feature maps. First the design and test results of a single processor chip are described. Based on these results a second chip has been developed implementing a 5 by 5 array of elements. Each processor has on-chip memory to store 64 weights of 8 Bit. The calculation unit has an internal precision of 14 Bit. An input pattern can have 64 vector components of 8 Bit. In order to achieve high speed, all elements work in parallel. Several of this chips can be cascaded to larger map sizes in a system.