Self-Organizing Maps
A High Performance SOFM Hardware-System
IWANN '97 Proceedings of the International Work-Conference on Artificial and Natural Neural Networks: Biological and Artificial Computation: From Neuroscience to Technology
A Scalable Processor Array for Self-Organizing Feature Maps
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
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A digital hardware implementation of self-organizing maps is presented. Dedicated hardware is implemented that allows the on-line visualization of the map during learning. The use of a scalable parallel architecture enables the realization of large scale high performance maps. Fist silicon was produced in a 0.8 mm, 2 metal layer CMOS technology, implementing about 161,800 transistors on a die size of 28.58 mm 2 . Experimental results are presented, that prove the functionality of the design up to a clock frequency of 40 MHz. A classification rate of 250,000 vectors per second and an adaptation rate of 94,000 vectors per second can be guaranteed, independent from the size of the network.