Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations

Authors:
Mario Porrmann;Ulf Witkowski;Heiko Kalte;Ulrich Rückert
Affiliations:
-;-;-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 5
Cited 2

Self-Organizing Maps

Self-Organizing Maps
Digital Connectionist Hardware: Current Problems and Future Challenges

IWANN '97 Proceedings of the International Work-Conference on Artificial and Natural Neural Networks: Biological and Artificial Computation: From Neuroscience to Technology
SOM Hardware with Acceleration Module for Graphical Representation of the Learning Process

MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Fault Detection and Isolation in Robotic Manipulators and the Radial Basis Function Network Trained by the Kohonen's Self-Organizing Map

SBRN '98 Proceedings of the Vth Brazilian Symposium on Neural Networks
Implementation of artificial neural networks on a reconfigurable hardware accelerator

EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing

FPGA implementation of a systems identification module based upon Hopfield networks

Neurocomputing
FPGA implementation of hopfield networks for systems identification

IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we discuss the usability of dynamic hardware reconfiguration for the simulation of neural networks. A dynamically reconfigurable hardware accelerator for self-organizing feature maps is presented. The system is based on the universal rapid prototyping system RAPTOR2000 that has been developed by the authors. The modular prototyping system is based on XILINX FPGAs and is capable of emulating hardware implementations with a complexity of more than 24 million system gates. RAPTOR2000 is linked to its host - a standard personal computer or workstation - via the PCI bus. For the simulation of self-organizing maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex (-E) series and optionally up to 128 MBytes of SDRAM. A speed-up of about 50 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing maps.