2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops
Neural Networks - 2005 Special issue: IJCNN 2005
Microprocessors & Microsystems
On automatic generation of VHDL code for self-organizing map
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A dynamically reconfigurable platform for self-organizing neural network hardware
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: models and applications - Volume Part II
Balancing guidance range and strength optimizes self-organization by silicon growth cones
ICANN'05 Proceedings of the 15th international conference on Artificial neural networks: formal models and their applications - Volume Part II
| Hi-index | 0.00 |
A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self-organizing feature maps, the hardware accelerates data pre- and postprocessing. For the verification of our architectural concepts in a real-world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.