2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops
Neural Networks - 2005 Special issue: IJCNN 2005
Microprocessors & Microsystems
On automatic generation of VHDL code for self-organizing map
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Implementation of a novel LVQ neural network architecture on FPGA
International Journal of Artificial Intelligence and Soft Computing
Fast optoelectronic neural network for vision applications
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
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This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-μm single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-μm digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor.