Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
The connection machine
A VLSI architecture for concurrent data structures
A VLSI architecture for concurrent data structures
Computer Vision, Graphics, and Image Processing
Data movement techniques for the pyramid computer
SIAM Journal on Computing
I.P. hierarchical systems: architectural features
Pyramidal systems for computer vision
Mesh-connected array processors with bypass capability for signal/image processing
Proceedings of the Twenty-First Annual Hawaii International Conference on Architecture Track
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
Meshes with reconfigurable buses
Proceedings of the fifth MIT conference on Advanced research in VLSI
Parallel algorithms for regular architectures: meshes and pyramids
Parallel algorithms for regular architectures: meshes and pyramids
Array processor with multiple broadcasting
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A pyramidal approach to parallel processing
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
The extension of object-oriented languages to a homogeneous, concurrent architecture
The extension of object-oriented languages to a homogeneous, concurrent architecture
Parallel Architectures and Algorithms for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
Processor autonomy on SIMD architectures
ICS '93 Proceedings of the 7th international conference on Supercomputing
Reconfigurable Buses with Shift Switching: Concepts and Applications
IEEE Transactions on Parallel and Distributed Systems
Designing Efficient Parallel Algorithms on CRAP
IEEE Transactions on Parallel and Distributed Systems
The DMBC: architecture and fundamental operations
ICS '95 Proceedings of the 9th international conference on Supercomputing
Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple Bus Networks
IEEE Transactions on Parallel and Distributed Systems
An Efficient Algorithm for Row Minima Computations on Basic Reconfigurable Meshes
IEEE Transactions on Parallel and Distributed Systems
Pc-based Shared Memory Architecture and Language
The Journal of Supercomputing
Image Processing on the OTIS-Mesh Optoelectronic Computer
IEEE Transactions on Parallel and Distributed Systems
A Fast Algorithm for k-Nearest Neighbor Problem on a Reconfigurable Mesh Computer
Journal of Intelligent and Robotic Systems
A Fast Parallel Algorithm for Convex Hull Problem of Multi-Leveled Images
Journal of Intelligent and Robotic Systems
Constant Time Sorting on Reconfigurable Meshes
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
On the Parallel Computation of the Algebraic Path Problem
IEEE Transactions on Parallel and Distributed Systems
Solving An Algebraic Path Problem and Some Related Graph Problems on a Hyper-Bus Broadcast Network
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Some Image Processing Algorithms on a RAP with Wider Bus Networks
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Time and work optimal simulation of basic reconfigurable meshes on hypercubes
Journal of Parallel and Distributed Computing
Journal of Intelligent and Robotic Systems
Computational models for image processing for shared-memory multiprocessors
Integrated Computer-Aided Engineering
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A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described. The architecture features a polymorphic-torus network which inserts an individually controllable switch into every node of the two-dimensional torus such that the network is dynamically reconfigurable to match the algorithm. Reconfiguration is accomplished by circuit switching and is achieved at fine-grained level. Using both the processor coordinate in the torus and the data for reconfiguration, the polymorphic-torus achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed. Implementation of the architecture is given to illustrate its VLSI efficiency.