Polymorphic-Torus Architecture for Computer Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
IEEE Transactions on Computers
Efficient histogramming on hypercube SIMD machines
Computer Vision, Graphics, and Image Processing
Meshes with reconfigurable buses
Proceedings of the fifth MIT conference on Advanced research in VLSI
Fast computer vision algorithms for reconfigurable meshes
Image and Vision Computing
IEEE Transactions on Parallel and Distributed Systems
Computing List Ranking on a RAP with Wider Bus Networks
Proceedings of the 1994 International Conference on Parallel and Distributed Systems
Computing Connected Components and Some Related Applications on a Rap
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 03
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Based on the reconfigurable array of processors with wider bus networks (Li et al., 1995), we propose a series of algorithms for image processing. Conventionally, only one bus is connected between two processors but in this machine it has a set of buses. Such a characteristic increases the computation power of this machine greatly. Based on the base-m number system, we first introduce some basic operation algorithms. Then three related applications are derived in constant time; one is the histogram of an image, another is the image segmentation and the other is the image labeling.