Designing Efficient Parallel Algorithms on CRAP

  • Authors:
  • Tzong-Wann Kao;Shi-Jinn Horng;Yue-Li Wang;Horng-Ren Tsai

  • Affiliations:
  • -;-;-;-

  • Venue:
  • IEEE Transactions on Parallel and Distributed Systems
  • Year:
  • 1995

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Abstract

A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several $O(1)$ time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the $k$th smallest element of $N$$m$ bits unsigned integers in $O(m)$ time using $N$ processors and to sort $N$ data items in $O(1)$ time using $O(N^{{5}\over{3}})$ processors instead of using $O(N^2)$ processors as those proposed by other researchers [2], [4], [8], [12], [17], respectively.Index Terms驴Prefix sum, selection, sort, parallel algorithms, cross-bridge, reconfigurable bus, reconfigurable array of processors.