Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
Parallel 2-D Convolution on a Mesh Connected Array Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence
Introducing local autonomy to processor arrays
Machine Vision: Algorithms, Architectures, and Systems
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Polymorphic-Torus Architecture for Computer Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
MIND execution by SIMD computers
Journal of Information Processing
Efficient parallelism using indirect addressing in SIMD processor arrays
Pattern Recognition Letters
Analysis of replicated data algorithms on processor array architectures
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Reconfigurable Processor-Array: A Bit-Sliced Parallel Computer
Reconfigurable Processor-Array: A Bit-Sliced Parallel Computer
Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
DAP—a distributed array processor
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Computational Aspects of VLSI
Interactive ray tracing on reconfigurable SIMD MorphoSys
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A low-cost mixed-mode parallel processor architecture for embedded systems
Proceedings of the 21st annual international conference on Supercomputing
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
FPGA-based fine-grain parallel computing (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
| Hi-index | 0.00 |
Flynn classified high speed (parallel) computers into four categories. Of these, the single instruction stream, multiple data stream (SIMD) processor array machines have become very popular in practical parallel processing. The commercially available processor array machines display important architectural variety, while belonging to SIMD category of machines. In this paper, we further categorize the SIMD class of machines on the basis of processor autonomy of the machines, which is the capability of the individual processing elements (PEs) to act autonomously in some significant way. For each autonomy class, we provide examples and illustrate some of its important algorithmic features. We also discuss how each type of autonomy can be simulated on machines without it. We study the addressing autonomous class of machines in greater detail by discussing three algorithms on machines with and without that type of autonomy. A discussion on how processor autonomy appears in algorithms in the literature and what impact they can have in the future machines also is provided.