Processor autonomy on SIMD architectures
ICS '93 Proceedings of the 7th international conference on Supercomputing
The UCSC Kestrel Parallel Processor
IEEE Transactions on Parallel and Distributed Systems
Finding the Next Computational Model: Experience with the UCSC Kestrel
Journal of Signal Processing Systems
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FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.