Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Communications of the ACM
Cell matrix methodologies for integrated circuit design
Integration, the VLSI Journal
Pushing the limits of standard CMOS
IEEE Spectrum
Multirate systems and filter banks
Multirate systems and filter banks
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
IEEE Transactions on Parallel and Distributed Systems
Asymptotic Limits of Video Signal Processing Architectures
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Tomorrow''s Digital Hardware will be Asynchronous and Verified
Tomorrow''s Digital Hardware will be Asynchronous and Verified
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
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VLSI chips suffer from exaggerated clock skew problems when the clock rate reaches several hundred MHz. To overcome this problem, back-propagating clock signals, the use of which is usually avoided (due to extended clock period) but known to be safe, can be exploited, resulting in a new pipelining method. We named this Counterflow-Clocked (C/sup 2/) Pipelining. The major advantages of this new method are: easier distribution of high speed clocks, shorter clock period due to the absence of global clock signals, natural use of dynamic latches, less internally generated noise due to uniformly distributed latch operations, etc. Composition rules were developed. The use of these rules enabled us to build a system with two-dimensional data-flow in C/sup 2/ pipelining employing a tree of inverter chains for clock distribution. C/sup 2/ pipelining was used to design an HDTV chip set with several design innovations, demonstrating the applicability and viability of the technology. This paper introduces C/sup 2/ pipelining and discusses its usefulness and limitations to build large and high speed VLSI chips. It also presents the design of an image compression chip set to implement subband vector quantization that can handle HDTV data rates with reasonable VLSI chip sizes.