Tomorrow''s Digital Hardware will be Asynchronous and Verified

Authors:
Alain J. Martin
Affiliations:
-
Venue:
Tomorrow''s Digital Hardware will be Asynchronous and Verified
Year:
1993

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Cited 1

High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

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Abstract

Encouraged by the results of almost a decade of research and experimentation, we claim that tomorrow''s design methods for digital VLSI will be based on a concurrent programming approach to high-level synthesis, asynchronous techniques, and correctness-preserving program transformations.