Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Highly parallel computing
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
PAX Computer; High-Speed Parallel Processing and Scientific Computing
PAX Computer; High-Speed Parallel Processing and Scientific Computing
Properties of Generalized Branch and Combine Clock Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
On the Complexity of Designing Optimal Branch-and-Combine Clock Networks
IEEE Transactions on Computers
Developing Micropipeline Wavefront Arbiters
IEEE Design & Test
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Theory of Generalized Branch and Combine Clock Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
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A scheme for global synchronization of arbitrarily large computing structures such thatclock skew between any two communicating cells is bounded above by a constant isdescribed. The scheme utilizes clock nodes that perform simple processing on clocksignals to maintain a constant skew bound irrespective of the size of the computingstructure. Among the salient features of the scheme is the interdependence betweennetwork topology, skew upper bound, and maximum clocking rate achievable. A 2-D mesh framework is used to present the concepts, introduce three network designs, and toprove some basic results. For each network the (constant) upper bound on clock skewbetween any two communicating processors, is established, and its independence ofnetwork size is shown. Simulations were carried out to verify correctness and to checkthe workability of the scheme. A 4*4 network was built and successfully tested forstability. Such issues as node design, clocking of nonplanar structures such ashypercubes, and the concept of fuse programmed clock networks are addressed.