Distributed mutual exclusion on a ring of processes
Science of Computer Programming
Analysis of interconnection networks with different arbiter designs
Journal of Parallel and Distributed Computing
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
A family of routing and communication chips based on the Mosaic
Proceedings of the 1993 symposium on Research on integrated systems
The Post Office experience: designing a large asynchronous chip
Integration, the VLSI Journal - Special issue on asynchronous systems
Symbolic Model Checking
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Introduction to VLSI Systems
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
IEEE Transactions on Parallel and Distributed Systems
Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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The author based asynchronous circuit realizations of symmetric crossbar arbiters on the paradigm of intercepting moving wavefronts in a two-dimensional micropipeline-like structure. The LockC component, a hybrid of a Muller C element and a Q flop, supports both the movement of wavefronts in the array and the ability to intercept wavefronts asynchronously. These arbiters may find use in multiprocessor routing networks whose characteristics better match the capabilities of asynchronous circuits.