Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Communications of the ACM
An Upper Bound on Expected Clock Skew in Synchronous Systems
IEEE Transactions on Computers
Comparison of tree and straight-line clocking for long systolic arrays
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Superconducting single flux quantum circuits using the residue number system
Superconducting single flux quantum circuits using the residue number system
Introduction to VLSI Systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation3
ICS '99 Proceedings of the 13th international conference on Supercomputing
A transduction-based framework to synthesize RSFQ circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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Rapid Single Flux Quantum (RSFQ) logic is a digital circuittechnology based on superconductors that has emerged as a possiblealternative to advanced semiconductor technologies for large scaleultra-high speed, very low power digital applications. Timing ofRSFQ circuits at frequencies of tens to hundreds of gigahertz is achallenging and still unresolved problem. Despite the manyfundamental differences between RSFQ and semi- conductor logic at thedevice and at the circuit level, timing of large scale digitalcircuits in both technologies is principally governed by the samerules and constraints. Therefore, RSFQ offers a new perspective onthe timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing,from the viewpoint of the principles, concepts, and languagedeveloped for semiconductor VLSI. It includes RSFQ clockingschemes, both synchronous and asynchronous, which have beenadapted from semiconductor design methodologies as well as thosedeveloped specifically for RSFQ logic. The primary features ofthese synchronization schemes, including timing equations, arepresented and compared.In many circuit topologies of current medium to large scale RSFQcircuits, single-phase synchronous clocking outperformsasynchronous schemes in speed, device/area overhead, andsimplicity of the design procedure. Synchronous clocking of RSFQcircuits at multigigahertz frequencies requires the application ofnon-standard design techniques such as pipelined clocking andintentional non-zero clock skew. Even with these techniques, thereexist difficulties which arise from the deleterious effects ofprocess variations on circuit yield and performance. As a result,alternative synchronization techniques, including but not limitedto asynchronous timing, should be considered for certain circuittopologies. A synchronous two-phase clocking scheme for RSFQcircuits of arbitrary complexity is introduced, which for criticalcircuit topologies offers advantages over previous synchronous andasynchronous schemes.