Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Authors:
Baris Taskin;Ivan S. Kourtev
Affiliations:
Department of Electrical Engineering, School of Engineering, University of Pittsburgh, Pittsburgh, PA;Department of Electrical Engineering, School of Engineering, University of Pittsburgh, Pittsburgh, PA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 8
Cited 2

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Abstract

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing [1] and nonzero clock skew scheduling [2] are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method [3] and the generated problems are solved using the industrial LP solver CPLEX [4]. The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew.