Understanding retiming through maximum average-weight cycles
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
| Hi-index | 0.00 |
In this paper we investigate properties of retiming, a circuit transformation which preserves the behavior of the circuit as a whole. We present an algorithm which transforms a given combinational circuit into a functionally equivalent pipelined circuit with minimum latency and clock-period no greater than a given upper bound c. The algorithm runs in O (E ) steps, where E is the number of interconnections in the circuit, and is optimal within a constant factor. We give a novel and concise characterization of the minimum clock-period of a circuit in terms of the maximum delay-to-register ratio cycle in the circuit. We show that this ratio does not exceed the minimum feasible clock-period by more than the maximum delay D of the elements in the circuit. This characterization leads to an O (E lg D) algorithm for minimum clock-period pipelining of combinational circuitry with latency no greater than a given upper bound l, an O (min{V E lg(V D), V E }) algorithm for minimum clock-period retiming of unit-delay circuitry, an O (V E lg D) algorithm for minimum clock-period retiming of general circuitry and an O (min{V E lg(V W ) lg (V D), V E lg (V D)}) algorithm for approximately minimum clock-period retiming, where V is the number of processing elements in the circuit. We demonstrate the closed semiring structure of retiming on unit-delay circuits under a given clock-period constraint. Finally, we give an O (V lg V ) algorithm for a mixed-integer optimization problem which arises in the linear programming framework of retiming.