Communications of the ACM
The Design and Evaluation of an Asynchronous Microprocessor
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Bridging Faults in Pipelined Circuits
Journal of Electronic Testing: Theory and Applications
A cell and macrocell compiler for GaAs VLSI full-custom design
Proceedings of the conference on Design, automation and test in Europe
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In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropiplined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.