Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Proceedings of the IEEE International Test Conference 2001
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test of Interconnection Opens Considering Coupling Signals
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines
ATS '07 Proceedings of the 16th Asian Test Symposium
On tests to detect via opens in digital CMOS circuits
Proceedings of the 45th annual Design Automation Conference
Automatic Test Pattern Generation for Interconnect Open Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
A bridging fault model where undetectable faults imply logic redundancy
Proceedings of the conference on Design, automation and test in Europe
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a nonrobust fault model.