On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Sequential Redundancy Identification Using Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
On Redundancy and Fault Detection in Sequential Circuits
IEEE Transactions on Computers
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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This paper presents a novel fault-independent algorithm for identifying untestable faults in sequential circuits. The algorithm is based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is untestable. It uses implications to find a subset of such faults whose detection requires conflicts on certain lines in the circuit. No global reset state is assumed and no state transition information is needed. Our fault-independent algorithm identifies untestable faults without any search as opposed to exhaustive search done by fault-oriented test generation algorithms. Results on benchmark and real circuits indicate that we find a large number of untestable faults, much faster (up to 3 orders of magnitude) than a test-generation-based algorithm that targeted the faults identified by our algorithm. Moreover, many faults identified as untestable by our approach were aborted when targeted by a sequential test generator.