On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
ITC'94 Proceedings of the 1994 international conference on Test
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On achieving complete testability of synchronous sequential circuits with synchronizing sequences
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 0.00 |
We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The cedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.