Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On achieving a complete fault coverage for sequential machines using the transition fault model
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Sequential Redundancy Identification Using Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On the Initialization of Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier in [1]. In this work, we give a detailed procedure based on the concepts of [1] and give experimental results of its application.