Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Functional test generation for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
| Hi-index | 0.00 |
One of the primary draw-backs of the core-based design paradigm is the limited knowledge of the internal structure and organization of the cores which is provided to the users. This problem is particularly critical from the point of view of testing, since it forces the designers to rely on the test patterns provided by the core vendors. As a solution that avoids the use of scan-based techniques, we present a test methodology which provides the following capabilities: Test generation for a system containing cores, and testability estimation and improvement of the system components. The methodology can be applied to designs consisting of an arbitrary interconnection of modules, some of which may be cores. Our approach relies on a fault model which allows the identification of an accurate correspondence between functional and stuck-at sources of failure. In addition, a functional DfT technique reduces the design to a feedback-free interconnection eventually improving the testability of some modules. This provides an abstraction of the interconnection structure of the system, thus enabling its simplification to a chain of three basic entities: The module under test, a controlling network, and an observing network. The whole methodology exploits the expressiveness of Binary Decision Diagrams for the storage and the manipulation of the system description. Some promising results, conducted on a reasonably complex core-based design, demonstrate the applicability of the proposed approach.