Symbolic optimization of FSM networks based on sequential ATPG techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
Implicit test pattern generation constrained to cellular automata embedding
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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This paper presents a new testing atmtegy for networks of interacting FSMa. The approach allows us to generate test patterns for faults in the network by separately handling the network's components. The proposed algorithms are fully symbolic; therefore, they allow the manipulation of large designs. Experimental results, though preliminary, are promising.