FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The digital circuit rewiring technique has been shown to be one of the most powerful logic transformation methods being able to further improve some already excellent results on many EDA problems. In this work a new hybrid rewiring approach that can enjoy advantages from both ATPG-based and graph-based rewiring is proposed. Our hybrid approach utilizes structural characteristics and ATPG technique to perform quick alternative wires identification inside circuits. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wires coverage when compared with ATPG-based rewiring engine with 4% of runtime only. For some problems only requiring a good-enough and very quick solution, this new rewiring technique may serve as a useful alternative.