A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A redesign technique for combinational circuits based on gate reconnections
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Fast post-placement rewiring using easily detectable functional symmetries
Proceedings of the 37th Annual Design Automation Conference
Design rewiring based on diagnosis techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
On applying erroneous clock gating conditions to further cut down power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Almost every wire is removable: a modeling and solution for removing any circuit wire
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 2.88 |
Let w"t be a wire in a combinational Boolean network. There may exist a wire w"a such that when w"a is added and w"t is removed, the overall circuit functionality is unchanged. Redundancy-addition-and-removal (RAR) is an efficient technique to find such a w"a. The idea is to add a redundant alternative wire w"a to make the target wire w"t redundant. However, as long as the addition of w"a together with the removal of w"t does not change the overall functionality of the circuit, wires that are added and removed do not necessarily need to be redundant. This raises a question about the existence of alternative wires. Why can one wire replace another wire in a combinational Boolean network? In this paper, we analyze theoretically the existence of alternative wires and model it as an error-cancellation problem. The two existing rewiring techniques, the redundancy-addition-and-removal and the global flow optimization, are unified under the proposed generalized model.