A redesign technique for combinational circuits based on gate reconnections

Authors:
Yuji Kukimoto;Masahiro Fujita;Robert K. Brayton
Affiliations:
University of California, Berkeley, CA;Fujitsu Laboratories of America, San Jose, CA;University of California, Berkeley, CA
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

Citing 3
Cited 3

The Transduction Method-Design of Logic Networks Based on Permissible Functions

IEEE Transactions on Computers
Rectification method for lookup-table type FPGA's

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Incremental Synthesis for Engineering Changes

ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors

Engineering change in a non-deterministic FSM setting

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Engineering change for power optimization using global sensitivity and synthesis flexibility

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Theory of wire addition and removal in combinational Boolean networks

Microelectronic Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Boolean-constraint problem and give a BDD-based algorithm to check the feasibility of redesign.