Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Gravity: Fast placement for 3-D VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
Proceedings of the 2005 international workshop on System level interconnect prediction
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Three-dimensional place and route for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a wirelength-driven force-directed three-dimension (3-D) Field Programmable Gate Arrays (FPGA) placement algorithm (3D-WFP) is presented. The algorithm is composed of three stages: Overlap permitted force-directed 2-D placement, legalization and 3-D layer partition. Different from traditional partition-based 3-D placers, we adjust the layer partition process after the 2-D global placement, which effectively provides the global interconnection and timing information for the next two sub-steps. To legalize the position of the logic block, a 3-D space filling curve is adopted. A low temperature simulated annealing (SA) is used to determine the blocks final layer. Only blocks with the same horizontal coordinate are permitted to interchange, the speed of the SA is very fast. Compared to recently publish 3-D FPGA placement work, this algorithm improves the half perimeter wire-length (HPWL) by 8.57%, almost at the same time cost and keeps the same timing performance.