mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
VLSI legalization with minimum perturbation by iterative augmentation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
At advanced technology nodes, highly-optimized placements need careful post-processing to further reduce interconnect length or optimize resource distribution, and therefore, high-performance legalization and detailed placement steps are essential for performance. In the last decade, we observed impressive improvements both in quality and speed of academic placement algorithms, in part enabled by the availability of realistic benchmarks and common evaluation frameworks along the history of ISPD, DAC and ICCAD placement contests. However, most research innovations have heavily relied on improvement and extensions of global placement algorithms [4, 5, 8, 9, 12, 15]. Detailed placement has been often limited to mixing existing methods and local interconnect length recovery, and individual impacts and relative performances of different detailed placement algorithms remain unclear. The goal of the ICCAD-2013 detailed-placement contest is to address these issues. In this contest, we provide (i) a suite of realistic benchmarks derived from industrial ASIC including input legal placements to detailed placers, and (ii) an evaluation framework to specifically measure the impact of detailed placement optimizations. To judge the quality of resulting placements, we consider both Half-Perimeter Wirelength (HPWL) and placement density, and impose maximum cell displacement limitations to the detailed placers. We hope that a set of standardized benchmarks and an evaluation framework will further accelerate research in the area of detailed placement.