A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
| Hi-index | 0.03 |
The complexity and size of digital circuits have grown exponentially, and today's circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes, so that the circuit layout can be performed faster and with higher quality. This paper presents a deterministic net-reduction-based clustering algorithm called Net Cluster. The basic idea of the proposed technique is to put the emphasis on reducing the number of nets versus the number of cells, thereby capturing the natural clusters of a circuit. The proposed algorithm has proven a linear-time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning and wire length-driven placement. The numerical experiments on the ISPD98 benchmark suite for partitioning and the ICCAD 2004 benchmark suite for placement demonstrate that by applying Net Cluster as a preprocessing step, the performance of state-of-the-art multilevel partitioners and placers can be further improved