Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Verification of a Complex SoC: The PRO3 Case-Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
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The advent of deep sub-micron technologies has created a number of problems for existing design methodologies. Most prominent among them is the problem of timing closure, whereby design time is dramatically increased due to iterations between gate-level synthesis and physical design. It is well known that the heart of this problem lies in the use of wireload models based on wirelength statistics from legacy designs. Some technology projections in have suggested that wireload models will remain effective to block sizes on the order of 50k gates. This suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design. We analyze these effects and dependencies in detail in this paper, and draw some conclusions about the amount of physical information that is required for synthesis to be effective. Finally, we discuss the implications on hierarchical design flows, and propose a solution via physical prototyping.